One of the common elements required in electrical circuit devices is the simple pullup (or pulldown device) from an active device to one of the power supply buses. The pullup is simple if used to construct a circuit using discrete components, in that, all that is required is selecting a resistor of the desired resistance and tolerance, connecting it between an active device, such as an open collector transistor, and V.sub.cc and the transistor's output would be pulled up to V.sub.cc once the transistor is forward biased. With the advent of the integrated circuit (IC) however, fabricating a resistance onto a wafer substrate, such as silicon or gallium arsenide, takes special consideration particularly when resistivity and tolerances play an important part in circuit operation.
For example, as SRAMs have evolved from the small 4 Kb memory arrays to more densely packed array sizes, tolerances of pullup resistances (or pullup loads) had to be tightly current path between a memory cell pulldown transistor and the V.sub.SS power supply bus. In this manner the PMOS transistor could be gated on only when the desired line was to be pulled to V.sub.CC and turned off otherwise, thereby virtually eliminating leakage current and minimizing standby current for the SRAM device as a whole.
Ongoing efforts to improve active loads has brought about the development of thin film transistors (TFTs) in attempts to provide low leakage current as well as high noise immunity. The following two articles, hereby incorporated by reference, discuss TFT development in SRAMs. The first article is "A POLYSILICON TRANSISTOR TECHNOLOGY FOR LARGE CAPACITY SRAMs," by Ikeda et al., IEDM 1990, pp. 469-472. The second article is "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity," by Yamanaka et al., IEDM 1988, pp. 48-51.
The present invention, however, introduces a TFT that uses a chemical mechanical process (CMP) to form a poly plug used to form the bottom gate thereby leaving the processed wafer substantially flat prior to TFT gate dielectric deposition and for all future photo/etch steps.